View ADP2102YCPZ-08-R7_3759602.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low duty cycle, 600 ma, 3 mhz synchronous step-down dc-to-dc converter adp2102 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features input voltage range: 2.7 v to 5.5 v 600 ma maximum load current 95% efficiency low duty cycle operation only 3 tiny external ceramic components 3 mhz typical operating frequency fixed output voltage from 0.8 v to 1.875 v adjustable output voltage up to 3.3 v 0.01 a shutdown supply current automatic power save mode internal synchronous rectifier internal soft start internal compensation enable/shutdown logic input undervoltage lockout current limit protection thermal shutdown small 8-lead, 3 mm 3 mm lfcsp package applications usb powered devices wlan and gateways point of loads processor core power from 5 v digital cameras pdas and palmtop computers portable media players, gps general description the adp2102 is a synchronous step-down dc-to-dc converter that converts a 2.7 v to 5.5 v unregulated input voltage to a lower regulated output voltage with up to 95% efficiency and 1% accuracy. the low duty cycle capability of the adp2102 is ideal for usb applications or 5 v systems that power up submicron subvolt processor cores. its 3 mhz typical operating frequency and excel- lent transient response allow the use of small, low cost 1 h inductors and 2.2 f ceramic capacitors. at medium-to-high load currents, it uses a current mode, pseudofixed frequency pulse- width modulation to extend battery life. to ensure the longest battery life in portable applications, the adp2102 has a power save mode (psm) that reduces the switching frequency under light load conditions to significantly reduce quiescent current. the adp2102 is available in both fixed and adjustable output voltage options with 600 ma maximum output current. the preset output voltage options voltage are 1.875 v, 1.8 v, 1.5 v, 1.375 v, 1.25 v, 1.2 v, 1.0 v, and 0.8 v. the adjustable voltage option is available from 0.8 v to 3.3 v. the adp2102 requires only three external components and consumes 0.01 a in shutdown mode. the adp2102 is available in an 8-lead lfcsp package and is specified for the ?40 c to +85 c temperature range. typical performance characteristics efficiency (%) 10 100 1000 load current (ma) 06631-052 v out = 1.375v t a = 25c v in = 2.7v v in = 4.2v v in = 3v 60 65 70 75 80 85 90 95 100 v in = 3.6v figure 1. typical applications circuit c in 2.2f 1h l c out 2.2f output voltage 0.8v to 1.875v input voltage 2.7v to 5.5v forced ccm dcm/ ccm on off 06631-001 adp2102 lx fb/out v in mode en gnd figure 2.
adp2102 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical performance characteristics ............................................. 1 typical applications circuit ............................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 boundary condition .................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 13 control scheme .......................................................................... 13 constant on-time timer ......................................................... 13 forced continuous conduction mode ................................... 13 power save mode ........................................................................ 13 synchronous rectification ........................................................ 14 current limit .............................................................................. 14 soft start ...................................................................................... 15 enable........................................................................................... 15 undervoltage lockout ............................................................... 15 thermal shutdown .................................................................... 15 applications information .............................................................. 16 inductor selection ...................................................................... 16 input capacitor selection .......................................................... 16 output capacitor selection ....................................................... 16 typical applications circuits .................................................... 17 setting the output voltage ........................................................ 19 efficiency considerations ......................................................... 19 thermal considerations ............................................................ 20 design example .......................................................................... 20 circuit board layout recommendations ................................... 22 recommended layout ............................................................... 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 9/07rev. a to rev. b changes to features, applications, and general description .... 1 changes to table 4............................................................................ 5 changes to table 6.......................................................................... 17 changes to table 7.......................................................................... 19 changes to circuit board layout recommendations section.... 21 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 23 6/07rev. 0 to rev. a changes to ordering guide .......................................................... 23 6/07revision 0: initial version
adp2102 rev. b | page 3 of 24 specifications v in = 3.6 v, en = v in , mode = v in , t a = 25c, unless otherwise noted. bold values indicate ?40c t a +85c. 1 table 1. parameter conditions min typ max unit input characteristics input voltage range 2 2.7 5.5 v undervoltage lockout threshold v in rising 2.2 2.4 2.5 v undervoltage lockout hysteresis 220 mv output characteristics output voltage range adp2102-xx 0.8 1.875 v output voltage range adp2102-adj 0.8 3.3 v output voltage initial accuracy adp2102-xx, t a = 25c, i load = 0 ma ?1 +1 % adp2102-xx, ?40c t a 85c, i load = 0 ma ?2 +2 % load regulation v out = 0.8 v to 1.875 v, i load = 0 ma to 600 ma 0.5 % line regulation v in = 2.7 v to 5.5 v, i load = 10 ma 0.3 % feedback characteristics fb regulation voltage adp2102-adj 784 800 816 mv fb bias current adp2102-adj, adp2102-0.8 50 na fb impedance adp2102-xx 375 k current characteristics operating current adp2102 psm mode, i load = 0 ma 70 99 a shutdown current en = 0 v 0.01 1 a output current adp2102, v in = 2.7 v to 5.5 v 600 ma lx (switch node) characteristics lx on resistance p-channel switch, i lx = 100 ma 325 600 m n-channel synchronous rectifier, i lx = 100 ma 200 400 m lx leakage current v in = 5.5 v, v lx = 0 v, 5.5 v 1 a lx minimum off-time adp2102-xx, adp2102-adj 100 ns lx on-time adp2102-0.8 55 87 105 ns adp2102-1.0 70 107 135 ns adp2102-1.2 100 131 160 ns adp2102-1.25 103 133 169 ns adp2102-1.375 135 165 195 ns adp2102-1.5 150 182 210 ns adp2102-1.8 180 220 260 ns adp2102-1.875 190 237 270 ns adp2102-adj-1.2 80 131 170 ns adp2102-adj-1.5 155 177 210 ns adp2102-adj-1.875 200 226 275 ns adp2102-adj-3.3 (v in = 5 v) 198 238 270 ns valley current limit 1 a enable, mode characteristics en, mode input high threshold 1.3 v en, mode input low threshold 0.4 v en, mode input leakage current v in = 5.5 v, en = mode = 0 v, 5.5 v 1 a soft start period 250 500 800 s thermal characteristics thermal shutdown threshold 150 c thermal shutdown hysteresis 15 c 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 the input voltage (v in ) range over which the rest of the specifications are valid. the part operates as expected until v in goes below the uvlo threshold.
adp2102 rev. b | page 4 of 24 absolute maximum ratings table 2. parameter rating avin, en, mode, fb/out to agnd ?0.3 v to +6 v lx to pgnd ?0.3 v to (v in + 0.3 v) pvin to pgnd ?0.3 v to +6 v pgnd to agnd ?0.3 v to +0.3 v avin to pvin ?0.3 v to +0.3 v operating ambient temperature range ?40c to +85c 1 junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 1 the adp2102 can be damaged when junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t is within the specified temperature limits. in applic ations where high power dissipation and poor thermal resistance are pres ent, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t ) of the device is dependent on the ambient temperature (t ), the power dissipation of the device (pd), and the junction-to-ambient thermal resistance of the package ( ). maximum junction temperature (t ) is calculated from the ambient temperature (t ) and power dissipation (p d) using the formula t = t + ( pd ). j j a ja j a j a ja unless otherwise specified, all other voltages ar e referenced to agnd. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. specified value of ja is based on a 4-layer, 4 in 3 in, 2 1/2 oz copper board, as per jedec standards. for more information, see application note an-772 , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . table 3. thermal resistance package type ja unit 8-lead lfcsp 54 c/w maximum power dissipation 0.74 w boundary condition natural convection, 4-layer board, exposed pad soldered to pcb. esd caution
adp2102 rev. b | page 5 of 24 pin configuration and fu nction descriptions 06631-003 1 mode 2 en 3 fb/out 4 agnd 8avin 7pvin 6lx 5pgnd adp2102 top view (not to scale) figure 3. pin configuration table 4. pin function descriptions pin o. nemonic description 1 mode mode input. to set the adp2102 to forced continuous co nduction mode (ccm), drive mode high. to set the adp2102 to power save mode/auto mode (psm), drive mode low. 2 en enable input. drive en high to turn on the adp2102. drive en low to turn it off and reduce the input current to 0.1 a. this pin cannot be left floating. 3 fb/out output sense input or feedback input. for fixed output versions, out is the top of the internal resistive voltage divider. connect out to the output voltage. for adjustable (n o suffix) versions, fb is the input to the error amplifier. drive fb through a resistive voltage divider to set the output voltage. the fb regulation threshold is 0.8 v. 4 agnd analog ground. connect agnd to pgnd at a single point as close to the adp2102 as possible. the exposed paddle is electrically common with the analog ground pin. 5 pgnd power ground. 6 lx switch output. lx is the drain of the p-channel mosfet switch and the n-channel synchronous rectifier. connect the output lc filter between lx and the output voltage. 7 pvin power source input. drive pvin with a 2.7 v to 5.5 v power source. a ceramic bypass capacitor of 2.2 f or greater is required on this pin to the nearest pgnd plane. 8 avin power source input. avin is the supply for the adp2102 internal circuitry. this pin can be connected in three different ways. for noise reduction, place an external rc filter be tween pvin and avin. the recommended values for the external rc filter are 10 and 0.1 f, respectively . this configuration can be used for all loads. for light-to-medium loads up to 300 ma, the avin pin and the pvin pin can be shorted together. for light-to-heavy loads (greater than 300 ma), bypass the avin pin with a 1 pf to 0.01 f capacitor to the nearest pgnd plane. do not shor t the avin and pvin pins when using only a bypass capacitor.
adp2102 rev. b | page 6 of 24 typical performance characteristics v in = 3.6 v, l = 2.2 h, c in = 2.2 f, c out = 4.7 f, unless otherwise noted. 100 95 90 85 80 75 70 65 60 efficiency (%) 1 10 100 1000 load current (ma) 06631-004 v in = 2.7v v in = 4.5v v in = 3.6v t a = 25c mode = psm l = 2.2h c in = 2.2f c out = 10f figure 4. efficiency vs. load current (v out = 1.2 v) 100 95 90 85 80 75 70 65 60 efficiency (%) 1 10 100 1000 load current (ma) 06631-005 v in = 2.7v v in = 4.5v v in = 3.6v t a = 25c mode = psm l = 2.2h c in = 2.2f c out = 10f figure 5. efficiency vs. load current (v out = 1.5 v) 100 95 90 85 80 75 70 65 60 efficiency (%) 1 10 100 1000 load current (ma) 06631-006 v in = 2.7v v in = 4.5v v in = 3.6v t a = 25c mode = psm l = 2.2h c in = 2.2f c out = 10f figure 6. efficiency vs. load current (v out = 1.8 v) 06631-007 1.22 1.21 1.20 1.19 1.18 output voltage (v) 0 100 200 300 400 500 600 load current (ma) v in = 2.7v v in = 4.5v v in = 3.6v t a = 25c figure 7. output voltage accuracy (v out = 1.2 v) 06631-020 1.52 1.51 1.50 1.49 1.48 output voltage (v) 0 100 200 300 400 500 600 load current (ma) v in = 2.7v v in = 4.5v v in = 3.6v t a = 25c figure 8. output voltage accuracy (v out = 1.5 v) 06631-009 1.82 1.81 1.80 1.79 1.78 output voltage (v) 0 100 200 300 400 500 600 load current (ma) v in = 2.7v v in = 4.5v v in = 3.6v t a = 25c figure 9. output voltage accuracy (v out = 1.8 v)
adp2102 rev. b | page 7 of 24 06631-050 100 95 90 85 80 efficiency (%) 1 10 100 1000 load current (ma) v in = 5.0v v in = 5.5v v in = 4.5v t a = 25c c ff = 6.8pf mode = psm figure 10. efficiency vs. load current (v out = 3.3 v) 95 90 85 80 75 70 65 60 55 50 efficiency (%) 10 100 1k load current (ma) 06631-026 psm ccm t a = 25c figure 11. psm vs. ccm efficiency (v out = 1.8 v) 06631-011 1.22 1.21 1.20 1.19 1.18 output voltage (v) 0 100 200 300 400 500 600 load current (ma) psm ccm t a = 25c figure 12. output voltage vs. load current (v out = 1.2 v) 06631-013 1.53 1.52 1.51 1.50 1.49 1.48 output voltage (v) 0 100 200 300 400 500 600 load current (ma) psm ccm t a = 25c figure 13. output voltage vs. load current (v out = 1.5 v) 06631-017 1.84 1.83 1.82 1.81 1.80 1.79 1.78 output voltage (v) 0 100 200 300 400 500 600 load current (ma) psm ccm t a = 25c figure 14. output voltage vs. load current (v out = 1.8 v) 06631-046 1.23 1.22 1.21 1.20 1.19 1.18 output voltage (v) ?45 ?25 ?5 15 35 55 75 temperature (c) i load = 0ma i load = 300ma i load = 600ma figure 15. output volt age vs. temperature (v out = 1.2 v)
adp2102 rev. b | page 8 of 24 1.52 1.51 1.50 1.49 1.48 1.47 1.46 ?40 ?15 10 35 60 85 temperature (c) 06631-047 output voltage (v) i load = 0ma i load = 300ma i load = 600ma figure 16. output volt age vs. temperature (v out = 1.5 v) 1.81 1.80 1.79 1.78 1.77 1.76 ?40 ?15 10 35 60 85 temperature (c) 06631-048 output voltage (v) i load = 0ma i load = 300ma i load = 600ma figure 17. output volt age vs. temperature (v out = 1.8 v) 06631-049 3.40 3.36 3.32 3.28 3.24 3.20 output voltage (v) 0 100 200 300 400 500 600 load current (ma) +85c +25c ?40c figure 18. output voltage accuracy (v out = 3.3 v) 85 80 75 70 65 60 quiescent current (a) 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 input voltage (v) 06631-045 +85c +25c ?40c figure 19. quiescent current vs. input voltage 76 75 74 73 72 71 70 77 quiescent current (a) ?40 ?20 0 20 40 60 80 100 120 temperature (c) 06631-053 figure 20. quiescent current vs. temperature 0.8005 0.8000 0.7995 0.7990 0.7985 0.7980 0.7975 0.7970 0.7965 ?50 0 50 100 temperature (c) v in = 3.6v 06631-021 feedback voltage (v) figure 21. feedback voltage vs. temperature
adp2102 rev. b | page 9 of 24 06631-051 4.5 4.0 3.5 3.0 2.5 2.0 1.5 switching frequency (mhz) 0 100 200 300 400 500 600 load current (ma) 0.8v 1.5v 1.8v 1v 1.25v 1.375v 1.875v 1.2v t a = 25c figure 22. switching frequency vs. load current 1.08 1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00 current limit (a) 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 input voltage (v) 06631-029 t a = 25c figure 23. valley current limit 400 350 300 250 200 150 100 50 0 switch on resistance (m ? ) 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 input voltage (v) pmos switch nmos switch 06631-027 t a = 25c figure 24. switch on resistance vs. input voltage 350 300 250 200 150 100 50 0 400 switch on resistance (m ? ) ?40 ?20 0 20 40 60 80 100 120 temperature (c) 06631-054 pmos switch nmos switch figure 25. switch on resistance vs. temperature 06631-014 ch1 500ma ? ch4 2.00v ch2 2.00v m 1.00s a ch4 2.76v b w b w b w 4 1 2 t t 51.00% ch1: il ch2: v out ch4: lx t a = 25c figure 26. psm mode operation at very light loads (10 ma) 06631-022 ch1 50.0mv ch3 50.0ma ? m 100s a ch3 86.0ma b w b w 1 3 t ccm ch1: v out ch3: il t a = 25c psm psm figure 27. psm mode entryexit operation (10 ma to 50 ma to 10 ma)
adp2102 rev. b | page 10 of 24 06631-015 ch1 500ma ? ch4 2.00v ch2 2.00v m 10.0s a ch4 2.72v b w b w b w 4 1 2 t t 51.00% ch1: il ch2: v out ch4: lx t a = 25c figure 28. psm mode operation at light loads (75 ma) 06631-016 ch1 200ma ? ch3 2.00v m 200ns a ch1 388ma b w b w ch4 2.00v b w 4 3 1 t t ?4.00000ns ch1: il ch4: v out ch3: lx t a = 25c figure 29. ccm mode operation at medium/heavy loads (0.3 a) 06631-031 ch1 2.00v ch2 100ma ? m 200s a ch2 82.0ma b w 2 1 3 t ch3 1.00v b w ch2: il ch3: v out ch1: lx t a = 25c v in = 3.6v v out = 1.5v i load = 0ma - 75ma - 0ma 0ma 0ma 75ma figure 30. light load behavior 180 160 140 120 100 80 60 40 20 0 psm threshold (ma) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) 06631-028 t a = 25c v out = 1.5v v out = 1.375v l = 2.2h figure 31. typical psm threshold vs. input voltage 06631-023 ch1 50.0mv ch2 200ma ? m 100s a ch2 220ma b w 1 2 t t 23.60% ch1: v out (ac) ch2: i load (0ma to 300ma) t a = 25c figure 32. load transient response (v out = 1.2 v) 06631-024 ch1 50.0mv ch2 200ma ? m 100s a ch2 236ma b w 2 1 t ch1: v out (ac) ch2: i load (0ma to 300ma) t a = 25c figure 33. load transient response (v out = 1.5 v)
adp2102 rev. b | page 11 of 24 06631-025 ch1 50.0mv ch2 200ma ? m 100s a ch2 264ma b w 1 2 t t ?300.000s ch1: v out (ac) ch2: i load (0ma to 300ma) t a = 25c figure 34. load transient response (v out = 1.8 v) 06631-032 ch1 50.0mv m 200s a ch3 3.74v b w 1 3 t ch3 1.00v b w ch1: v out (ac) ch3: v in (3v to 4v step) t a = 25c figure 35. line transient response (v out = 1.2 v) 06631-035 ch1 50.0mv m 100s a ch3 3.72v b w 1 3 t ch3 1.00v b w ch1: v out (ac) ch3: v in (3v to 4v step) t a = 25c figure 36. line transient response (v out = 1.5 v) 06631-044 ch1 50.0mv m 40.0s a ch3 3.70v b w 1 3 t ch3 1.00v b w ch1: v out (ac) ch3: v in (3.6v to 4.2v step) t a = 25c figure 37. line transient response (v out = 1.8 v) 06631-019 ch1 200ma ? ch4 2.00v ch2 1.00v m 20.0ms a ch3 2.00v b w b w b w 4 2 1 t t 14.60% ch1: lx ch2: v out ch4: en t a = 25c figure 38. start-up and shutdown waveform 06631-030 ch1 2.00v ch2 500mv m 400s a ch1 1.40v b w b w 2 3 1 t t 27.60% ch3 200ma ? b w ch2: v out ch1: v in ch3: lx t a = 25c figure 39. light load start-up waveform
adp2102 rev. b | page 12 of 24 06631-033 ch1 2.00v ch2 500mv m 2.00ms a ch2 350mv b w b w 2 1 3 t t 6.600% ch3 200ma ? b w ch3: il ch2: v out ch1: en t a = 25c figure 40. heavy load start-up waveform 06631-034 ch1 2.00v m 2.00s a ch1 4.20v b w 1 4 t t 51.00% ch4 20.00mv b w t a = 25c ch4: v out (ac) ch1: lx l = 2.2h c in = 2.2f c out = 4.7f figure 41. psm mode ripple (v in = 3.6 v, load = 50 ma) 06631-018 ch1 5.00v ch4 500ma ? ch3 1.00v m 1.00s a ch3 440mv b w b w b w 3 1 4 ch1: lx ch2: v out ch4: il t a = 25c figure 42. short-circuit response at output 06631-055 ch3 200ma ? m 100s a ch4 680mv b w 3 4 t ch4 500mv b w t a = 25c ch4: v out ch3: il t 43.40% v in = 3.6v v out = 1.375v c out = 4.7f i load = 100ma figure 43. soft start waveform
adp2102 rev. b | page 13 of 24 theory of operation the adp2102 is a high frequency, synchronous step-down, dc-to-dc converter optimized for battery-powered, portable applications. it is based on constant on-time current-mode control architecture with voltage feed forward to null frequency variation with line voltage, creating a pseudofixed frequency. this type of control allows generation of very low output voltages at a higher switching frequency and offers a very fast load and line transient response with minimal external component count and size. the adp2102 provides features such as undervoltage lockout, thermal shutdown, and short-circuit protection. the adp2102 uses valley current-mode control, which helps to prevent minimum on-time limitations at very low output voltages. this allows high frequency operation, resulting in low filter inductor and capacitor values. control scheme the adp2102 high-side power switch on-time is determined by a one-shot timer whose pulse width is directly proportional to the output voltage and inversely proportional to the input or line voltage. another one-shot timer sets a minimum off time to allow for inductor valley current sensing. the constant on-time, one-shot timer is triggered at the rising edge of en and, subsequently, when the low-side power switch current is below the valley current limit threshold and the minimum off-time one-shot timer has timed out. while the constant on-time is asserted, the high-side power switch is turned on. this causes the inductor current to ramp positively. after the constant on-time has completed, the high- side power switch turns off and the low-side power switch turns on. this causes the inductor current to ramp negatively until the sensed current flowing in this switch has reached valley current limit. at this point, the low-side power switch turns off and a new cycle begins with the high-side switch turning on, provided that the minimum off-time one shot has timed out. constant on-time timer the constant on-time timer sets the high-side switch on-time. this fast, low jitter, adjustable one shot varies the on-time in response to input voltage for a given output voltage. the high- side switch on-time is inversely proportional to the input voltage and directly proportional to the output voltage. t on = k ( v out / v in ) (1) the duty cycle for a buck converter operating in continuous conduction mode (ccm) is given by d = v out /v in and, by definition, d = t on /(t on + t off ). therefore, equating the duty cycle terms of v out /v in and t on /(t on + t off ) gives t on = v out /( v in f sw ) (2) equating equation 1 and equation 2 gives f sw = 1/ k (3) where k is an internally set on-time scale factor constant resulting in a constant switching frequency. as shown in equation 1, the steady state switching frequency is theoretically independent of both the input and output voltages to a first order. this means the loop switches at a nearly constant frequency until a load step occurs. when a load step occurs, the constant on-time control loop responds by modulating the off time up or down to quickly return to regulation. this momentary frequency variation results in a faster load transient response than a fixed frequency current-mode control loop of similar bandwidth with a similar external filter inductor and capacitor. this is an advantage of a constant on-time control scheme. resistive voltage losses in the high-side and low-side power switches, package parasitics, inductor dcr, and board parasitic resistance cause the loop to compensate by reducing the off time and, therefore, increase the switching frequency with increasing load current. a minimum off-time constraint is introduced to allow inductor valley current sensing on the synchronous switch. forced continuous conduction mode when the mode pin is high, the adp2102 operates in forced continuous conduction mode (ccm). in this mode, irrespective of the load current, the inductor current stays continuous, and ccm is the preferred mode of operation for low noise applications. during this mode, the switching frequency stays close to 3 mhz typical. in this mode, efficiency is lower at light loads, compared to the power save mode, but the output voltage ripple is minimized. power save mode when the mode pin is low, the adp2102 operates in power save mode (psm). in this mode, at light load currents, the part automatically goes into reduced frequency operation where some pulses are skipped to increase efficiency while remaining in regulation. at light loads, a zero-crossing comparator truncates the low-side switch on-time when the inductor current becomes negative. in this condition, the part works in discontinuous conduction mode (dcm). the threshold between ccm and dcm is approximately i load (skip) = sw in out out in fvl vvv ? 2 ) ( (4) there is a first-order dependency of this threshold on the internally set on-time scale factor indicated in equation 3. for higher load currents, the inductor current does not cross zero threshold. the device switches to the continuous conduction mode, and the frequency is fixed to the nominal value.
adp2102 rev. b | page 14 of 24 as a result of this auto mode control technique, losses are minimized at light loads, improving system efficiency. when the load current is further increased such that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease to this threshold before the next on-time begins. the psm reverse current comparator controls the entry and exit into forced continuous conduction mode. some minor jitter is normal during transition from dcm to ccm with loads at approximately 100 ma typical, and it has no adverse impact on regulation. both v out and the switching frequency are reduced as the circuit operates in constant current mode. the load current (i ocl ) under these conditions is equal to the current limit threshold plus half the ripple current, as shown in equation 5 and in figure 44 . synchronous rectification i ocl = i valley + i l /2 (5) in addition to the p-channel mosfet switch, the adp2102 includes an integrated n-channel mosfet synchronous recti- fier. the synchronous rectifier improves efficiency, especially at low output voltages, and reduces cost and board space by eliminating the need for an external rectifier. dc current limit = max load inducto r current i valley current limit time 06631-036 i ocl current limit the current limit circuit employs a valley current sensing scheme. current limit detection occurs during the off time through sensing of the voltage drop across the on resistance of the synchronous rectifier switch. the detection threshold is 1 a typical. figure 44. valley current limit figure 45 illustrates the inductor current waveform during normal operation and during current limit. the output current, i out , is the average of the inductor ripple current waveform. the low-to-medium load current waveform illustrates the continuous conduction mode operation with peak and valley inductor currents below the current limit threshold. when the load current is increased, the ripple waveform maintains the same amplitude and frequency because the current falls below the current limit threshold at the valley of the ripple waveform. as the current falls below the threshold during the normal off- time of each cycle, the start of each on-time is not delayed, and the circuit output voltage is regulated at the correct value. the ripple current is calculated using equation 6. i l = lfv vvv sw in out in out uu u ) ( (6) the adp2102 also provides a negative current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced continuous conduction mode. under negative current limit conditions, both the high- side and low-side switches are disabled. i peak i ocl i valley i medium load current high load current current limit normal operation inductor current current limit threshold 06631-037 i out figure 45. inductor current?current limit operation
adp2102 rev. b | page 15 of 24 soft start the adp2102 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, therefore limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. enable the device starts operation with soft start when the en pin is toggled from logic low to logic high. pulling the en pin low forces the device into shutdown mode, with a typical shutdown current of 0.01 a. in shutdown mode, both the high-side and low-side power switches are turned off, the internal resistor feed- back divider is disconnected, and the entire control circuitry is switched off. for proper operation, the device is in shutdown mode when voltage applied to this pin is less than 0.4 v and enabled when voltage applied is greater than 1.3 v. this pin must not be left floating. undervoltage lockout the undervoltage lockout circuit prevents the device from operating incorrectly at low input voltages. it prevents the converter from turning on the main switch and the synchronous switch under undefined conditions and, therefore, prevents deep discharge of the battery supply. thermal shutdown when the junction temperature, t j , exceeds 150c typical, the device goes into thermal shutdown. in this mode, the high- side and low-side power switches are off. the device resumes operation when the junction temperature again falls below 135c typical. 06631-038 s r q reverse current comparator current sense amplifier min off-timer regulation comparator error amplifier internal compensation on-time timer rise- detect bandgap reference uvlo pvin mode a vin lx pgnd agnd fb/out en thermal shutdown r r non- overlapping drivers 8 1 7 5 6 2 3 4 fixed adjustable figure 46. internal block diagram
adp2102 page 16 of 24 applications information the external component selection for the adp2102 applications circuit, as shown in figure 2, is driven by the load requirement and begins with the selection of inductor l. once the inductor is chosen, c in and c out can be selected. inductor selection the high switching frequency of the adp2102 allows for minimal output voltage ripple, even with small inductors. inductor sizing is a trade-off between efficiency and transient response. a small inductor leads to a larger inductor current ripple that provides excellent transient response but degrades efficiency. due to the high switching frequency of the adp2102, multilayer ceramic inductors can be used for an overall smaller solution size. shielded ferrite core inductors are recommended for their low core losses and low electromagnetic interference (emi). as a guideline, the inductor peak-to-peak current ripple, i l , is typically set to 1/3 of the maximum load current for optimal transient response and efficiency. i l = l f v v v v sw in out in out ? ) ( 3 ) ( max load i (7) l ideal = ) ( 3 . 0 ) ( max load sw in out in out i f v v v v ? where f sw is the switching frequency. finally, it is important that the inductor be capable of handling the maximum peak inductor current, i pk , determined by the following equation: i pk = i load(max) + i l /2 (8) the dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. table 5 shows some typical surface mount inductors that work well in adp2102 applications. input capacitor selection the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. the rms input current flowing through the input capacitor is, at maximum, i out /2. select an input capacitor capable of with- standing the rms input current for the maximum load current in the application to be used. i rms = i outmax in out in out v v v v ) ( ? (9) the input capacitor reduces input voltage ripple caused by the switch currents on the pvin pin. place the input capacitor as close as possible to the pvin pin. in principle, different types of capacitors can be considered, but for battery-powered applications, the best choice is a multilayer ceramic capacitor, due to its small size and equivalent series resistance (esr). it is recommended that the pvin pin be bypassed with a 2.2 f or larger ceramic input capacitor. the size of the input capacitor can be increased without any limit for better input voltage filtering. x5r or x7r dielectrics are recommended, with a voltage rating of 6.3 v or 10 v. y5u and z5u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. in applications with greater than 300 ma load current, a ceramic bypass capacitor of 0.01 f is recommended on the avin pin for better regulation performance. output capacitor selection the output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. for a given loop crossover frequency (the frequency at which the loop gain drops to 0 db), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. the adp2102 is designed to operate with small ceramic capacitors that have low esr and equivalent series inductance (esl) and are thus comfortably able to meet tight output voltage ripple specifications. x5r or x7r dielectrics are recommended with a voltage rating of 6.3 v or 10 v. y5v and z5u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. when choosing output capacitors, it is also important to account for the loss of capacitance due to output voltage dc bias. if ceramic output capacitors are used, the capacitor rms ripple current rating should always meet the application requirements. the rms ripple current is calculated as i rms(cout) = 3 2 1 max in sw out max in out v f l v v v _ _ ) ( ? (10) at nominal load currents, the converter operates in forced continuous conduction mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor esr plus the voltage ripple caused by charging and discharging the output capacitor. v out = i l (esr + 1/ (8 c out f sw )) (11) the largest voltage ripple occurs at the highest input voltage, v in . at light load currents, the converter operates in power save mode, and the output voltage ripple is dependent on the output capacitor value. the adp2102 control loop is stable with a ceramic output capacitor of 2.2 f. for better transient performance, a 10 f ceramic capacitor is recommended at the output. table 6 lists input and output mlcc capacitors recommended for adp2102 applications.
adp2102 rev. b | page 17 of 24 table 5. recommended inductor selection manufacturer series value (h) dcr () current rating (ma) size (l w h) (mm) fdk corporation mipf2520d 2.2 0.08 1300 2.5 2.0 1.0 tdk mlp2520s2r2l 2.2 0.08 1300 2.5 2.0 1.0 murata lqm2hpn2r2mj0 2.2 0.13 1000 2.5 2.0 1.1 coilcraft, inc. lps3015-222ml 2.2 0.11 1500 2.9 2.9 1.5 taiyo yuden nr3010t2r2m 2.2 0.10 1100 3.0 3.0 1.0 table 6. recommended input and output capacitor selection capacitor murata taiyo yuden tdk vishay 2.2 f 6.3 v x5r 0603 grm188r60j225k jmk107bj225ka c1608x5r0j225m 4.7 f 6.3 v x5r 0603 grm188r60j475k jmk107bj475ka c1608x5r0j475m 10 f 6.3 v x5r 0603 grm188r60j106m jmk107bj106ma c2012x5r0j106m 0.01 f 25 v x7r 0402 grm155r71e103ka01d tmk105bj103kv-f c1005x7r1e103k 1 pf 50 v x7r 0402 gjm1554c1h1r0jb01c vj0402a1r2cxacw1bc 6.8 pf 25 v x7r 0402 vj0402a6r8kxaa typical applications circuits 0 6631-039 l1 2.2h c out 2.2f c in 2.2f 1 2 3 4 8 7 6 5 mode en fb/out agnd avin pvin lx pgnd adp2102-fxd gnd output voltage = 0.8v to 1.875v input voltage = 2.7v to 5.5v v out v in figure 47. adp2102-fxd (0 ma i load 300 ma) 06631-008 l1 2.2h c out 4.7f c bp 0.01f c in 2.2f 1 2 3 4 8 7 6 5 mode en fb/out agnd avin pvin lx pgnd adp2102-fxd gnd output voltage = 0.8v to 1.875v input voltage = 2.7v to 5.5v v out v in figure 48. adp2102-fxd (0 ma i load 600 ma)
adp2102 rev. b | page 18 of 24 06631-040 c out 4.7f c in 2.2f 1 2 3 4 8 7 6 5 mode en fb/out agnd avin pvin lx pgnd adp2102-adj v out gnd output voltage = 0.8v to 3.3v v in input voltage = 2.7v to 5.5v c ff r1 r2 l1 2.2h note *c ff is needed for adjustable v out > 1.875v only. see table 7 for adjustable v out configurations. * figure 49. adp2102-adj (0 ma i load 300 ma) 06631-012 c ff r1 r2 l1 2.2h c out 4.7f c bp 0.01f c in 2.2f 1 2 3 4 8 7 6 5 mode en fb/out agnd avin pvin lx pgnd adp2102-adj gnd output voltage = 0.8v to 3.3v input voltage = 2.7v to 5.5v v out v in * note *c ff is needed for adjustable v out > 1.875v only. see table 7 for adjustable v out configurations. figure 50. adp2102-adj (0 ma i load 600 ma)
adp2102 rev. b | page 19 of 24 setting the output voltage the output voltage of the adp2102-adj is externally set by a resistive voltage divider from the output voltage to fb. the ratio of the resistive voltage divider sets the output voltage, and the absolute value of those resistors sets the divider string current. for lower divider string currents, the small 10 na (50 na maximum) fb bias current should be taken into account when calculating resistor values. the fb bias current can be ignored for a higher divider string current, but doing so degrades the efficiency at very light loads. for the adp2102-adj, the equation for output voltage selection is v out = v fb (1 + r 1 / r 2 ) (12) where: v out is the output voltage. v fb is the feedback voltage, 0.8 v. r 1 is the feedback resistor from v out to fb. r 2 is the feedback resistor from fb to gnd. for any adjustable output voltage greater than 1.875 v, a feed- forward capacitor must be added across r1 for better transient performance and stability. the formula for calculation of c1 is c ff = 1/(2 r1 f co /2) (13) for example, in a 5 v to 3.3 v application, if a 4.7 f capacitor is used at the output, a 6.8 pf feed-forward capacitor is recom- mended. the output capacitor value dictates the loop crossover frequency, f co . for an output capacitor of 4.7 f, the loop crossover frequency is 150 khz. the high frequency zero created by c ff and r1 can be very important for transient load applications. capacitor c ff provides phase lead and functions as a speed-up capacitor to output voltage changes, so it tends to short out r1 and improve the high frequency response. this zero tends to produce a positive-going bump in the phase plot. ideally, the peak of this bump is centered over the crossover frequency of the loop. the r1 and c ff zero is located at f z = 1/(2 r1 c ff ) (14) the adp2102-xx (where xx represents the fixed output voltage) includes the resistive voltage divider internally, reducing the external circuitry required. for improved load regulation, connect the fb/out to the output voltage as close as possible to the load. for more information about the adp2102-adj configurations for v out , see table 7 . table 7. adp2102-adj configurations for v out v out (v) r 1 (k) r 2 (k) c ff (pf) l (h) c in (f) c out (f) 0.8 1 80.6 none 2.2 2.2 4.7 1.0 20 100 none 2.2 2.2 4.7 1.2 49.9 100 none 2.2 2.2 4.7 1.25 56.2 100 none 2.2 2.2 4.7 1.375 71.5 100 none 2.2 2.2 4.7 1.5 88.7 100 none 2.2 2.2 4.7 1.8 124 100 none 2.2 2.2 4.7 1.875 133 100 none 2.2 2.2 4.7 2.0 150 100 15 2.2 2.2 4.7 2.5 215 100 10 2.2 2.2 4.7 3.0 274 100 8.2 2.2 2.2 4.7 3.3 316 100 6.8 2.2 2.2 4.7 efficiency considerations efficiency is defined as the ratio of output power to input power. the high efficiency of the adp2102 has two distinct advantages. first, only a small amount of power is lost in the dc-to-dc converter package that reduces thermal constraints. in addition, high effi- ciency delivers the maximum output power for the given input power, extending battery life in portable applications. following are the four major sources of power loss in dc-to-dc converters like the adp2102: ? power switch conduction losses ? inductor losses ? switching losses ? transition losses power switch conduction losses power switch conduction losses are caused by the flow of output current through the p-channel power switch and the n-channel synchronous rectifier, which have internal resistances (r ds(on) ) associated with them. the amount of power loss can be approxi- mated by p sw_cond = ( r ds (on)_p d + r ds (on) _n (1 ? d )) i out 2 (15) where d = v out / v in . the internal resistance of the power switches increases with temperature but decreases with higher input voltage. figure 24 in the typical performance characteristics section shows the change in r ds (on) vs. input voltage, and figure 25 shows the change in r ds (on) vs. temperature for both power devices.
adp2102 rev. b | page 20 of 24 inductor losses inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (dcr) associated with it. larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losses are related to the magnetic permeability of the core material. because the adp2102 is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low emi. the total amount of inductor power loss can be calculated by p l = dcr i out 2 + core losses (16) switching losses switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. each time a power device gate is turned on and turned off, the driver transfers a charge q from the input supply to the gate and then from the gate to ground. the amount of power loss can be calculated by p sw = ( c gate_p + c gate_n ) v in 2 f sw (17) where: c gate_p is the gate capacitance of the internal high-side switch. c gate_n is the gate capacitance of the internal low-side switch. f sw is the switching frequency. transition losses transition losses occur because the p-channel switch cannot turn on or turn off instantaneously. in the middle of an lx node transition, the power switch provides all the inductor current. the source to drain voltage of the power switch is half the input voltage, resulting in power loss. transition losses increase with load current and input voltage and occur twice for each switching cycle. the amount of power loss can be calculated by p tran = v in /2 i out ( t r + t f ) f sw (18) where: t r is the rise time of the lx node. t f is the fall time of the lx node. thermal considerations in most applications, the adp2102 does not dissipate a lot of heat, due to its high efficiency. however, in applications with maximum loads at high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is great enough that it may cause the junction temperature of the die to exceed the maximum junction temperature of 125c. once the junction temperature exceeds 150c, the converter goes into thermal shutdown. it recovers only after the junction temperature has decreased to below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application solution is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, shown in the following equation: t j = t a + t r (19) where: t j is the junction temperature. t a is the ambient temperature. t r is the rise in temperature of the package due to power dissipation in it. the rise in temperature of the package is directly proportional to the power dissipation in the package. the proportionality constant for this relationship is defined as the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: t r = ja p d (20) where: t r is the rise in temperature of the package. ja is the thermal resistance from the junction of the die to the ambient temperature of the package. p d is the power dissipation in the package. design example the calculations in this section provide only a rough estimate and are no substitute for bench evaluation. consider an application where the adp2102 is used to step down from 3.6 v to 1.8 v with an input voltage range of 2.7 v to 4.2 v. v out = 1.8 v @ 600 ma pulsed load = 300 ma v in = 2.7 v to 4.2 v (3.6 v typical) f sw = 3 mhz (typical) t a = 85c inductor i l = lfv vvv sw in out in out ? ) ( 3 )( max load i = 0.6/3 = 200 ma l = )( 3.0 )/1( max load sw inmax out out if vv v ? = )6.03.0103( )2.4/8.11(8.1 6 ? = 1.90 h choose a 2.2 h inductor for this application. i pk = i load(max) + i l /2 = 0.6 + 0.2/2 = 0.7 a p l = i outmax 2 dcr = (0.6 a) 2 0.08 (fdk mipf2520d) = 29 mw
adp2102 rev. b | page 21 of 24 output capacitor for transient applications, assume a droop of 0.1 v. typically, it takes two to three cycles for the output to settle from a load transient because the capacitor alone supplies the load current until the loop responds. under these conditions, a minimum required output capacitance is calculated as follows: c out_min = 3 sw droop load f v i = 6 1031.0 3.03 = 3 f choose a 4.7 f capacitor for this application. for an instantaneous step decrease in load current, the output capacitor required to limit the output voltage overshoot (v os ) during a full load to no load transient must be determined. this transient requires the excess energy stored in the output inductor to be absorbed by the output capacitor with a limited overshoot in the output voltage. assuming an overshoot of 50 mv for a full load transient, c out = 2 2 2 ) ( out os out out vvv il ?+ = 2 2 2 )8.1()85.1( )6.0(h2.2 ? = 4.33 f choose a 4.7 f capacitor for this application. i rms = 32 1 max in sw out maxin out vfl vvv _ _ ) ( ? = 32 1 2.4103102.2 )8.12.4(8.1 6 6 ? ? = 45 ma rms p cout = i rms 2 esr = (0.045) 2 0.005 = 10.12 w input capacitor assume an input ripple of 27 mv based on 1% of v in_min. for ceramic capacitors, the typical esr is from 5 m to 15 m. c in = sw out in f esriv ? 4) /( 1 = 6 1034)005.06.0/027.0( 1 ? = 2.2 f i rms = i out /2 = 0.3 a rms p cin = i rms 2 esr = (0.3) 2 0.005 = 450 w losses p sw_cond = ( r ds (on)_p d + r ds (on)_n (1 ? d )) i out 2 = (0.310 0.5 + 0.145 0.5) (0.6) 2 = 82 mw p tran = ( v in /2) i out ( t r + t f ) f sw = (3.6/2) 0.6 (5 ns + 5 ns) 3 10 6 = 32.4 mw p sw = ( c gate_p + c gate_n ) v in 2 f sw = (200 pf) (3.6) 2 3 10 6 = 7.8 mw p l = dcr i out 2 = 0.08 (0.6) 2 = 28.8 mw p loss = p sw_cond + p tran + p sw + p l = 82 mw + 32.4 mw + 7.8 mw + 28.8 mw = 151 mw t jmax = t a + ja p loss = 85c + 54c/w 151 mw = 93.15c p loss is well below the junction temperature maximum of 125c.
adp2102 rev. b | page 22 of 24 circuit board layout recommendations good circuit board layout is essential in obtaining the best performance from the adp2102. poor circuit layout degrades the output ripple and regulation, as well as the emi and electromagnetic compatibility performance. figure 52 and figure 53 show the ideal circuit board layout for the typical applications circuit shown in figure 48 . use this layout to achieve the highest performance. refer to the following guidelines for optimum layout: ? use separate analog and power ground planes. connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. in addition, connect the ground references of power components, such as input and output capacitors, to power ground. connect both ground planes to the exposed pad of the adp2102. ? place the input capacitor as close to the pvin pin as possible and connect the other end to the closest power ground plane. ? for low noise and better transient performance, a filter is recommended between pvin and avin. place the 0.1 f, 10 low-pass input filter between the avin pin and the pvin pin, as close to avin as possible; or the avin pin can be bypassed with a 1 pf capacitor to the nearest gnd plane. ? ensure that the high current loops are as short and as wide as possible. make the high current path from c in through l, c out , and the pgnd plane back to c in as short as possible. to accomplish this, ensure that the input and output capacitors share a common pgnd plane. in addition, make the high current path from the pgnd pin through l and c out back to the pgnd plane as short as possible. to do this, ensure that the pgnd pin of the adp2102 is tied to the pgnd plane as close as possible to the input and output capacitors. ? place the feedback resistor divider network as close as possible to the fb pin to prevent noise pickup. try to minimize the length of trace connecting the top of the feedback resistor divider to the output while keeping away from the high current traces and the switch node (lx) that can lead to noise pickup. to reduce noise pickup, place an analog ground plane on either side of the fb trace and make it as small as possible to reduce the parasitic capacitance pickup. recommended layout 06631-041 8 mm vout cout pgnd vin 9 mm mode en fb/out agnd l1 inductor cin cbp adp2102 figure 51. recommended pcb layout of the adp2102-fxd
adp2102 rev. b | page 23 of 24 06631-042 vout cout pgnd vin mode en fb/out agnd l1 inductor cin cbp adp2102 figure 52. recommended layout of the top layer of the adp2102-fxd application board 06631-043 vout pgnd mode en fb/out agnd vin figure 53. recommended layout of the bottom layer of the adp2102-fxd application board
adp2102 rev. b | page 24 of 24 outline dimensions 0 61507-b 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator seating plane 0.30 0.23 0.18 0.60 max 0.60 max figure 54. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters ordering guide model output current (ma) temperature range 3 output voltage package description package option branding adp2102ycpz-0.8-r7 1 600 ?40c to +85c 0.8 v 8-lead lfcsp_vd cp-8-2 l5t adp2102ycpz-1.0-r7 1 600 ?40c to +85c 1.0 v 8-lead lfcsp_vd cp-8-2 l5u adp2102ycpz-1.2-r7 1 600 ?40c to +85c 1.2 v 8-lead lfcsp_vd cp-8-2 l5v adp2102ycpz-1.25r7 1 600 ?40c to +85c 1.25 v 8-lead lfcsp_vd cp-8-2 l5w adp2102ycpz-1.37r7 1 600 ?40c to +85c 1.375 v 8-lead lfcsp_vd cp-8-2 l5x adp2102ycpz-1.5-r7 1 600 ?40c to +85c 1.5 v 8-lead lfcsp_vd cp-8-2 l5y adp2102ycpz-1.8-r7 1 600 ?40c to +85c 1.8 v 8-lead lfcsp_vd cp-8-2 l5z adp2102ycpz-1.87r7 1 600 ?40c to +85c 1.875 v 8-lead lfcsp_vd cp-8-2 l60 adp2102ycpz-1-r7 1 600 ?40c to +85c 0.8 v to 1.2 v 8-lead lfcsp_vd cp-8-2 l6k adp2102ycpz-2-r7 1 600 ?40c to +85c 1.2 v to 1.5 v 8-lead lfcsp_vd cp-8-2 l6l adp2102ycpz-3-r7 1 600 ?40c to +85c 1.5 v to 1.875 v 8-lead lfcsp_vd cp-8-2 l6m adp2102ycpz-4-r7 1 600 ?40c to +85c 2.5 v to 3.3 v 2 8-lead lfcsp_vd cp-8-2 l6n adp2102-0.8-evalz 1 fixed output 0.8 v evaluation board adp2102-1.0-evalz 1 fixed output 1.0 v evaluation board adp2102-1.2-evalz 1 fixed output 1.2 v evaluation board adp2102-1.25-evalz 1 fixed output 1.25 v evaluation board adp2102-1.375-evalz 1 fixed output 1.375 v evaluation board adp2102-1.5-evalz 1 fixed output 1.5 v evaluation board adp2102-1.8-evalz 1 fixed output 1.8 v evaluation board adp2102-1.875evalz 1 fixed output 1.875 v evaluation board adp2102-1-evalz 1 adjustable output 0.8 v to 1.2 v evaluation board adp2102-2-evalz 1 adjustable output 1.2 v to 1.5 v evaluation board adp2102-3-evalz 1 adjustable output 1.5 v to1.875 v evaluation board adp2102-4-evalz 1 adjustable output 2.5 v to 3.3 v evaluation board 1 z = rohs compliant part. 2 2.5 v to 3.3 v adjustable output voltage option is from 4.5 v < v in < 5.5 v only. 3 operating junction temperature range: ?40c to +125c. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06631-0-9/07(b)

▲Up To Search▲

Price & Availability of ADP2102YCPZ-08-R7

	To Download ADP2102YCPZ-08-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .